Monolithic integration of enhancement- and depletion-mode AlGaN/GaN HFETs

ABSTRACT

A method for and devices utilizing monolithic integration of enhancement-mode and depletion-mode AlGaN/GaN heterojunction field-effect transistors (HFETs) is disclosed. Source and drain ohmic contacts of HFETs are first defined. Gate electrodes of the depletion-mode HFETs are then defined. Gate electrodes of the enhancement-mode HFETs are then defined using fluoride-based plasma treatment and high temperature post-gate annealing of the sample. Device isolation is achieved by either mesa etching or fluoride-based plasma treatment. This method provides a complete planar process for GaN-based integrated circuits favored in high-density and high-speed applications.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority from U.S. Provisional PatentApplication 60/740,256 filed on Nov. 29, 2005, and also from U.S.Provisional Patent Application 60/748,339 filed on Dec. 8, 2005, both ofwhich are hereby incorporated by reference.

BACKGROUND AND SUMMARY OF THE INVENTION

The present application relates to a method for monolithic integrationof enhancement and depletion-mode heterojunction field effecttransistors (“HFETs”) , and in particular, to fabrication ofaluminum-gallium nitride/gallium nitride (“AlGaN/GaN”) HFETs using suchmonolithic integration.

Group III-nitride (“III-N”) compound semiconductors, such as thoseincorporating AlGaN/GaN, possess the advantages of having wide bandgap,high breakdown field, and large thermal conductivity, which can bringsignificant benefits to the design of heterostructure field-effecttransistors and applications utilizing HFETs. Because of their highpower handling capabilities, AlGaN/GaN HFETs can be used for radiofrequency/microwave power amplifiers and high power switches. However,most power amplifiers and switches using AlGaN/GaN HFETs featuredepletion-mode (“D-mode”) HFETs as the building block. Since a D-modeHFET is a transistor with a negative value for the threshold voltage(V_(th)), D-mode HFETs need both a positive and negative voltage bias tobe turned on and off. If an enhancement-mode (“E-mode”) HFET could bemade available, only a positive voltage supply would be needed forcircuit applications, resulting in simplified circuits and reducedcosts.

Furthermore, owing to the wide bandgap of the GaN-based semiconductormaterials, AlGaN/GaN HFETs are capable of high-temperature operation(potentially up to 600° C.), and are thus suitable for high-temperatureintegrated circuits such as required in aviation and automotiveapplications. Further, for HFET-based logic circuits, the direct-coupledfield effect transistor logic (“DCFL”) features the simplestconfiguration. In DCFLs, E-mode HFETs are used as drivers while D-modeHFETs are used as the load.

Note that at zero gate bias, a D-mode HFET is capable of conductingcurrent, and is called “normally-on” whereas for an E-mode HFET, thetransistor is not conducting current , and is called “normally-off”.

FIG. 1 shows an E-mode HFET 10 using a thin AlGaN barrier layer 12, anundoped GaN layer 18, and a substrate layer 20, such as can be made fromsapphire, silicon, or silicon carbide. With the help of the Schottkybarrier 14 between the gate metal 16 and the AlGaN barrier, the channelbetween source 22 and drain 24 can be pinched-off at zero gate bias aslong as the AlGaN barrier is thin enough. However, E-mode HFETsfabricated in this manner have poor performance characteristics, such aslow transconductance, large on-resistance, and high knee-voltage. Thisis due to high access resistance. As shown in FIG. 1, the access regionbetween the gate and source also has very low carrier density because ofthe thin AlGaN barrier. Thus, the access region is also in the E-mode,which needs positive bias to be turned on. To produce E-mode HFETs withlow access resistance, a “self-aligned” fabrication process is required,in which only the channel region directly under the gate electrode is inE-mode. Note that gates that are not self-aligned required overlap,which increases device size and stray capacitance.

There have been several attempts at fabrication of E-mode AlGaN/GaN highelectron mobility transistors (“HEMTs”). Note that the terms “HEMT” and“HFET” are synonymous. Both are field effect transistors with a junctionbetween two materials with different band gaps, e.g. a heterostructureas the channel. The effect of this heterostructure is to create a verythin layer where the Fermi energy is above the conduction band, givingthe channel very low resistance, e.g., “high electron mobility”. As withall the other types of FETs, a voltage applied to the gate alters theconductivity of the thin layer.

Using a thin AlGaN barrier (10 nm), Khan et al. produced an E-mode HEMTwith a peak transconductance of 23 mS/mm.

Another attempt to fabricate an E-mode HFET in an AlGaN/GaN system wasreported by Hu et al., “Enhancement mode AlGaN/GaN HFET with selectivelygrown PN junction gate,” April 2000, IEE Electronics Letters, Vol. 36,No. 8, pp. 753-754, which is hereby incorporated by reference in itsentirety. In this work a selectively-grown P/N junction gate is used.The selectively-grown P-type layer is able to raise the potential of thechannel and therefore deplete the carriers from the channel at zero gatebias. However, such an approach is not self-aligned and the problem oflarge access resistance persists.

Another attempt to fabricate an E-mode HFET in an AlGaN/GaN system wasreported by Moon et al. who used inductively coupled plasma reactive ionetching (“ICP-RIE”) to carry out gate recess-etching. See Jeong S. Moonet al., “Submicron Enhancement-Mode AlGaN/GaN HEMTs,” June 2002, Digestof 60th Device Research Conference, pp. 23-24, which is herebyincorporated by reference in its entirety.

Kumar el at. used a similar approach. Note that the AlGaN barrier underthe gate can be thinned by the recess-etching and the threshold voltageis then raised to a positive value. However, ICP-RIE can cause seriousdamage to the AlGaN barrier and results in increased gate leakagecurrent. To remove ICP-RIE induced damage, the recess-etching patternsmust be removed and followed by high-temperature (about 700° C.)annealing. Thus, the gate patterns have to be created again throughphoto-lithography which cannot be accurately aligned with therecess-etching windows previously generated in the gate recess stage.Therefore, the process requires double photolithography, or alignment,and is not self-aligned. To ensure that the recess windows are fullycovered by the gate electrodes, the gate electrodes need to be largerthan the recess windows, resulting in a larger gate size, as mentionedearlier. Another problem associated with the ICP-RIE etching is the pooruniformity in the etching depth, which is undesirable for integratedcircuits because it severely affects the uniformity in the thresholdvoltage.

Another approach used gate metals, e.g. Platinum (“Pt”) or Molybdenum(“Mo”), that have larger work function and have the tendency of reactingwith III/V compound semiconductors. (Work function refers to the energyrequired to release an electron as it passes through the surface of ametal.) For example, a Pt-based buried gate technology was previouslyused in realizing E-modeindium-aluminum-arsenide/indium-gallium-arsenide HFETs. For AlGaN/GaNHFETs, Endoh et al. created an E-mode HFET from a D-mode HFET with aPt-based gate electrode. Through high temperature gate annealing, thegate metal front can be made to sink into the AlGaN barrier andeffectively reduce the barrier thickness and raise the threshold voltageto a positive value. Such an approach requires a D-mode HFET with athreshold voltage already close to zero because the sinking depth of thePt-gate is limited. However, for monolithically-integrated E/D-mode HFETcircuits, it is desirable for the D-mode HFET (which serves as the load)to have a more negative threshold voltage.

U.S. Patent Application 20030218183 entitled “High Power-Low NoiseMicrowave GaN Heterostructure Field Effect transistor” to MiroslavMicovic et al., discloses a gate recess technique as one existingprocess technique to fabricate E-mode HFETs. However, in an AlGaN/GaNHFET, because of the lack of effective wet etching techniques, therecess etching is carried out by dry etching. For example, ICP-RIE isused for the recess etching, as mentioned earlier, with the accompanyingsevere damage and defects to the device.

U.S. Patent Application 2005059197 entitled “Semiconductor Device andMethod for Manufacturing the Same” to Yoshimi Yamashita et al.,discloses a technique using the approach of using gate metals withlarger work function for fabricating E-mode HFETs in GaN-based materialsystems. However, no metal has been found to have a work function largerthan 1 electron volt (“eV”). As a result, in order to fabricate anE-mode HFET using the method of Yamashita et al., a sample which alreadyexhibits a threshold voltage closer to zero volts is needed. This is notsuitable for the integration of E-mode and D-mode HEMTs, which are bothrequired for DCFL circuits.

The gate recess technique has also been used to implement monolithicintegration of E/D HFETs in AlGaN/GaN heterostructures. As describedabove, such approach requires a two-mask gate process, introducing extraprocess steps and cost as compared to a single-mask gate process.

To achieve high density and high-uniformity in the E/D HEMT integration,the three-dimensional mesas impose serious limits to photolithographyand interconnects. Thus, a planar process is desired, as seen from thesuccessful development of the commercial GaAs MESFET integratedcircuits.

Additionally, due to the lack of P-channel AlGaN/GaN HEMTs, a circuitconfiguration similar to the based on CMOS cannot be implemented atpresent. Using N-channel HEMTs, direct-coupled field-effect transistor(“FET”) logic (DCFL), as shown in FIG. 1A, which features integratedenhancement/depletion-mode (“E/D-mode”) HEMTs, offers the simplestcircuit configuration.

Because of the heretofore lack of a compatible integration process forboth D-mode and E-mode AlGaN/GaN HEMTs. Hussain et al. made a trade-offand used an all-D-mode-HEMT technolgoy and buffered FET logic (“BFL”)configuration to realize an inverter and a 31-stage ring oscillator thatincludes 217 transistors and two negative voltage supplies.

Based on low damage Cl₂-based ICP-RIE technology, Microvic et al.applied the technology of two-step gate recess etching and usedplasma-enhanced chemical vapor deposition (“PECVD”)-grown siliconnitride as the gate metal deposition mask to fabricate the E-mode GaNHEMTs, which are integrated with the D-mode GaN HEMT. They showed apropagation delay of 127 ps/stage at a drain bias voltage of 1.2 V for a31-stage DCFL ring oscillator with the 0.15-μm-gate technology.

Monolithic Integration of Enhancement-Mode and Depletion-Mode AlGaN/GaNHFETs

The present application sets forth devices, circuits, and systems withmonolithic integration of D-mode and E-mode HFETs, as well as methodsfor building them. In one class of embodiments, a patterned plasmatreatment is used to introduce a fixed charge into the wide-bandgapmaterial under the gates of only some devices. In this example, D-modeHFETs are defined without plasma treatment to the barrier layer underthe gate, and the E-mode HFETs are defined with plasma treatment to thebarrier layer under the gate.

The disclosed innovations in various embodiments, provide one or more ofat least the following advantages:

-   -   Allows for monolithic integration of enhancement-mode and        depletion-mode AlGaN/GaN HEMTs for the implementation of        complete circuits in DCFL or other logic families.    -   Provides a self-aligned approach to fabricating E/D-mode        AlGaN/GaN HEMTs with low on-resistance, low knee-voltage, and        high extrinsic transconductance.    -   Provides a method to manufacture self-aligned E/D-mode HFETs        using readily available microelectronic fabrication equipment.    -   Provides a method enabling the production of reproducible and        stable E/D-mode HEMT devices, particularly suitable for high        temperature digital circuit applications.    -   Provides for allowing large supply voltage in DCFL circuit to        improve the noise margin and to shorten gate delay.    -   Provides for large input voltage swings to eliminate the need        for logic level adjustment between adjacent stages in IC's.    -   Provides a planar integration for E/D-mode HEMTs without any        mesa etching or gate recess etching.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosed innovations will be described with reference to theaccompanying drawings, which show important sample embodiments of thepresent innovations and which are incorporated in the specificationhereof by reference, wherein:

FIG. 1 shows a prior art E-mode HFET.

FIG. 1A shows a DCFL circuit schematic for an E/D inverter.

FIG. 1B shows a DCFL circuit for a ring oscillator.

FIG. 1C shows a photomicrograph of an inverter as one embodiment of thepresent innovations.

FIG. 1D shows a photomicrograph of a ring oscillator as one embodimentof the present innovations.

FIG. 2 shows transfer characteristics of a conventional D-mode HEMT, anE-mode HEMT without the benefit of the present innovations, and oneembodiment of the present innovations.

FIGS. 3A through 3F show one embodiment of a process of fabricating anE-mode AlGaN/GaN HFET.

FIG. 4A shows I-V output characteristics for one embodiment of an E-modeAlGaN/GaN HFET.

FIG. 4B shows I_(g)-V_(gs) characteristics for one embodiment of anE-mode AlGaN/GaN HFET.

FIG. 5 shows fluorine ion concentration profiles as measured by “SIMS”for one embodiment of an E-mode AlGaN/GaN HFET.

FIG. 6 shows the cross section of one embodiment of the presentinnovations prior to implantation of fluorine ions.

FIG. 7 shows fluorine ion concentration profiles as measured by “SIMS”for various embodiments.

FIGS. 7A and 7B show fluorine ion concentration profiles as measured by“SIMS” for various embodiments.

FIG. 8A shows the I_(d) versus V_(gs) transfer characteristics of E-modeAlGaN/GaN HFETs after different CF₄ plasma-treatment conditions.

FIG. 8B shows the g_(m) versus V_(gs) transfer characteristics of E-modeAlGaN/GaN HFETs after different CF₄ plasma-treatment conditions.

FIG. 9 shows the extracted barrier heights and ideality factors of gateSchottky diodes with different CF₄ plasma treatments.

FIG. 10 shows the V_(th) dependence on plasma power and treatment timefor various E-mode AlGaN/GaN HFETs.

FIG. 11 shows an AFM image depicting the insignificant etching effect ofthe CF₄ plasma treatment on the AlGaN layer.

FIG. 12A shows the DC I_(d) versus V_(gs) transfer characteristics forvarious E-mode AlGaN/GaN HFET embodiments.

FIG. 12B shows the DC g_(m) versus V_(gs) transfer characteristics forvarious E-mode AlGaN/GaN HFET embodiments.

FIG. 13 shows the DC output characteristics for one E-mode AlGaN/GaNHFET embodiment.

FIG. 14A shows both reverse and forward gate currents with different CF₄plasma treatments for various embodiments of an E-mode AlGaN/GaN HFET.

FIG. 14B shows enlarged and forward gate currents with different CF₄plasma treatments for various embodiments of an E-mode AlGaN/GaN HFET.

FIG. 15 shows dependencies of f_(t) and f_(max) on gate bias, whereV_(ds) is fixed at 12V.

FIG. 16 shows on-wafer measured f_(t) and f_(max) with different CF₄plasma treatments.

FIGS. 17A through 17F show a sample process of fabricating an E-modeSi₃N₄AlGaN/GaN MISHFET.

FIG. 18 shows sample DC output characteristics.

FIG. 19A shows the transfer characteristics.

FIG. 19B shows gate leakage currents.

FIG. 20 shows pulse measurements.

FIG. 21 shows small signal RF characteristics.

FIG. 22 shows simulated conduction-band diagrams of conventional D-modeAlGaN/GaN HEMT without CF₄ plasma treatment.

FIG. 23 shows simulated conduction-band diagrams of an E-mode AlGaN/GaNHEMT with a CF₄ plasma treatment.

FIG. 24 shows the electron concentration of a conventional D-modeAlGaN/GaN HEMT without CF₄ plasma treatment and of an E-mode AlGaN/GaNHEMT with CF₄ plasma treatment.

FIG. 25 shows one embodiment for a process flow of monolithicintegration of E-mode and D-mode HEMTs for an inverter according to thepresent innovations.

FIGS. 26A through 26F show a sample process flow for monolithicintegration of E-mode and D-mode HFETs.

FIG. 27 shows a planar process flow for monolithic integration.

FIG. 28 shows another sample process flow for E/D-mode HEMTs.

FIG. 29 shows DC output characteristics of an D-HEMT and an E-HEMTfabricated by a planar process.

FIG. 30 compares transfer characteristics of the planar process withthose of a conventional process.

FIG. 31 shows static voltage transfer characteristics of an E/D HEMTinverter fabricated by a planar fabrication process.

FIG. 32 show an epitaxial structure for the HEMTs used in a sampleembodiment.

FIG. 33 show the integrated process flow of monolithic integration ofE-mode and D-mode HEMTs for a monolithic inverter.

FIG. 34 show sample geometry parameters for inverters and ringoscillators.

FIG. 35 show DC I-V transfer characteristics and output characteristicsof sample D-mode and E-mode AlGaN/GaN HEMTs as disclosed.

FIG. 36 shows performances of fabricated E- and D-mode AlGaN/GaN HEMTs.

FIG. 37 show I_(g)-V_(g) characteristics of both D- and E-mode HEMTs andsimulated conduction-edge band diagrams under the gate electrode for aD-mode HEMT and an E-mode HEMT.

FIG. 38 shows static voltage transfer characteristics for a conventionalE/D HEMT inverter.

FIG. 39 shows static voltage transfer characteristics of E/D HEMTinverters with β=6.7, 10, 25, and 50 according to various disclosedembodiments.

FIG. 40 shows noise margins for inverters with different beta values.

FIG. 41 shows static voltage transfer characteristics of E/D HEMTinverters with β=10 measured at different supply voltages.

FIG. 42 show noise margins measured at different V_(DD)'s for aninverter with β=10.

FIG. 43 shows load and input current of an inverter with β=10 atV_(DD)=2.5 V, according to a sample embodiment.

FIG. 44 shows a frequency spectrum, and

FIG. 45 shows time-domain characteristics, of a 17-stage ring oscillatorwith β=10 biased at V_(DD)=3.5 V.

FIG. 46 shows dependences of propagation delay and power-delay producton the supply voltage for one circuit embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The numerous innovative teachings of the present application will bedescribed with particular reference to the presently preferredembodiment (by way of example, and not of limitation).

FIGS. 3A through 3F illustrate the process of fabricating anenhancement-mode III-nitride HFET according to a first embodiment of thepresent innovations. FIG. 3A illustrates a preferred epitaxial structureof the present innovations, where the reference numerals 110, 120, 130and 140 denote substrate (e.g. sapphire, silicon or SiC), nucleationlayer (low temperature grown GaN nucleation layer, AlGaN or AlN), hightemperature-grown GaN buffer layer, and Al_(x)Ga_(1-x)N barrier layerincluding the modulation doped carrier supply layer. The manufacturingmethod of enhancement mode III-nitride HFET of one embodiment isdescribed below. The mesa isolation is formed using Cl₂/He plasma dryetching followed by the source/drain ohmic contact formation 160 withTi, Al, Ni and Au annealed at 850° C. for 45 seconds as shown in FIG.3B. Next, photoresist 170 is patterned with the gate windows exposed.Then, the fluorine ions are incorporated into Al_(x)Ga_(1-x)N barrierlayer by, for examples, either fluorine plasma treatment or fluorineions implantation as shown in FIG. 3C. The gate electrode 180 is formedon the barrier layer 140 by depositing and lift-off Ni and Au as shownin FIG. 3D. Thereafter, post-gate RTA is conducted at 400-450° C. for 10minutes. A passivation layer 190 is grown on the top of the wafer asshown in FIG. 3E. Finally, the contact pads are opened by removingportions of the passivation layer on the contact pads as shown in FIG.3F.

EXAMPLE 1

An AlGaN/GaN HEMT structure was grown on a (0001) sapphire substrate inan Aixtron AIX 2000 HT metal-organic chemical vapor deposition (MOCVD)system. The HEMT structure consists of a low-temperature GaN nucleationlayer, a 2.5-m-thick unintentionally doped GaN buffer layer and an AlGaNbarrier layer with nominal 30% Al composition. The barrier layerconsists of a 3-nm undoped spacer, a 15-nm carrier supplier layer dopedat 2.5×10¹⁸ cm⁻³, and a 2-nm undoped cap layer. Room temperature Hallmeasurements of the structure yield an electron sheet density of1.3×10¹³ cm⁻² and an electron mobility of 1000 cm²/Vs. The device mesawas formed using Cl₂/He plasma dry etching in an STS ICP-RIE systemfollowed by the source/drain ohmic contact formation with Ti/Al/Ni/Auannealed at 850° C. for 45 seconds. The ohmic contact resistance wastypically measured to be 0.8 ohm-mm.

After gate windows with 1 nm length were opened by contactphotolithography, the sample was treated by CF₄ plasma in an RIE systemat an RF plasma power of 150 W for 150 seconds. Pressure of thetreatment is typically 50 mTorr. The typical depth distribution profileof the fluorine ions thus incorporated via the treatment is Gaussian,and the typical depth when the fluorine concentration drops from thepeak by one order of magnitude is 20 nm. Note that ion implantation isanother method for incorporating the fluorine ions, and it is estimatedthat an energy of about 10 KeV would be required.

Ni/Au electron-beam evaporation and liftoff were carried outsubsequently to form the gate electrodes. The plasma treated gate regionand the gate electrode were self-aligned. Post-gate RTA was conducted at400° C. for 10 minutes. This RTA temperature was chosen because RTA attemperatures higher than 500° C. can degrade both the gate Schottkycontract and the source/drain ohmic contacts. The devices have asource-gate spacing of L_(sg)=1 μm and a gate-drain spacing of L_(gd)=2μm. D-mode HEMTs were also fabricated on the same sample without plasmatreatment to the gate regions.

FIG. 2 shows the transfer characteristics of both D-mode and E-mode(before and after post-gate annealing) AlGaN/GaN HEMTs. Defining V_(th)as the gate bias intercept of the linear extrapolation of drain currentat the point of peak transconductance (g_(m)), the V_(th) of the E-modedevice was determined to be 0.9 V, while the V_(th) of the D-mode deviceis −4.0 V. More than 4 V of V_(th) shift was achieved by the plasmatreatment. At V_(gs)=0, the transconductance reaches zero, indicating atrue E-mode operation. The drain current is well pinched-off and shows aleakage of 28 μA/mm at V_(ds)=6 V, the smallest value reported up todate for E-mode AlGaN/GaN HEMTs. The peak g_(m) is 151 mS/mm for theD-mode HEMT and 148 mS/mm for the E-mode HEMT, respectively. The maximumdrain current (I_(max)) reaches 313 mA/mm at the gate bias (V_(gs)) of 3V for the E-mode HEMT. Comparison of the current-voltage (I-V)characteristics of E-mode device before and after RTA suggests that RTAat 400° C. for 10 minutes plays an important role in recovering thedamages induced during the plasma treatment and achieving high currentdensity and transconductance. FIG. 4A shows the output curves of theE-mode device before and after the RTA process. No change in thresholdvoltage was observed after the RTA. At a V_(gs) of 2.5 V, the saturationdrain current (247 mA/mm) of E-mode device after RTA at 400° C. is 85%higher than that (133 mA/mm) before RTA, and the knee voltage of theE-mode device with RTA is 2.2 V, where the drain current is 95%saturation drain current. The off-state drain breakdown voltage atV_(gs)=0V is larger than 80 V, showing no degradation compared to thatobserved in the D-mode HEMTs. FIG. 4B shows I_(g)/V_(gs) curves of thesethree devices. Lower gate leakage currents were achieved for E-modeHEMT, especially after RTA.

In order to investigate the mechanisms of the V_(th) shift by CF₄ plasmatreatment, secondary ion mass spectrum (SIMS) measurements were carriedout on accompanying samples to monitor the atomic composition changes ofthe CF₄ plasma treated AlGaN/GaN materials. In addition to Al, Ga, andN, significant amount of fluorine atoms were detected in the plasmatreated sample. FIG. 5 shows the fluorine atom concentration profile ofthe sample treated at a CF₄ plasma power of 150 W for 2.5 minutes. Theconcentration of fluorine atoms is the highest near the AlGaN surfaceand drops by one order of magnitude in the channel. It can be deducedthat the fluorine ions produced by the CF₄ plasma were incorporated intothe sample surface, similar to the effects of plasma immersion ionimplantation (“PIII”), a technique developed to realize ultra-shallowjunctions in advanced silicon technology. Because of the strongelectro-negativity of the fluorine ions, the incorporated fluorine ionscan provide immobile negative charges in the AlGaN barrier andeffectively deplete the electrons in the channel. With enough fluorineions incorporated in the AlGaN barrier, the D-mode HEMT can be convertedto an E-mode HEMT. The CF₄ plasma treatment can result in a thresholdvoltage shift as large as 4.9 V. After RTA at 400° C. for 10 minutes,the peak fluorine atom concentration near the AlGaN surface is unchangedwhile that around the AlGaN/GaN interface experiences more significantreduction. It should be noted, however, SIMS measurement results fromdifferent runs do not offer accurate quantitative comparison because ofthe lack of reference criterion. Nevertheless, the minute change inV_(th) before and after RTA indicates that the total number of fluorineions incorporated into the AlGaN barrier is near constant before andafter RTA, while the plasma damages are significantly recovered by theRTA. The lower gate reverse leakage currents of an E-mode HEMT can beattributed to an upward band bending of the AlGaN layer as a result offluorine ion incorporation. After the RTA process, the defects at theinterface of metal and AlGaN induced by CF₄ were recovered, leading tofurther suppression of gate leakage current. From the atomic forcemicroscopy (“AFM”) measurement conducted on a patterned sample, it wasobserved that the plasma treatment only results in a 0.8 nm reduction inthe overall AlGaN barrier layer (20 nm thick).

On-wafer small-signal RF characteristics of D-mode and E-mode AlGaN/GaNHEMTs were measured from 0.1 to 39.1 GHz. The current gain and maximumstable gain/maximum available gain (MSG/MAG) of both types of deviceswith 1 μm-long gate were derived from measured S-parameters as afunction of frequency, as shown in FIG. 5. At V_(ds)=12 and V_(gs)=1.9V, a current gain cutoff frequency (f_(T)) of 10.1 GHz and a power gaincutoff frequency (f_(MAX)) of 34.3 GHz were obtained for the E-modeAlGaN/GaN HEMT, a little lower than that of its D-mode counterpart,whose and were measured at the drain bias of 12 V and gate bias of −3 Vto be 13.1 and 37.1 GHz, respectively.

One advantage of the present innovations is that the E-mode HFET withfluorine ions incorporated in barrier layer can stand a larger gate bias(>3V) corresponding to a larger input voltage swing.

Also, thermal reliability testing has shown that the fluorine ionincorporation in the AlGaN barrier is stable up to 700° C. However, theSchottky contact, made of nickel, is only stable up to 500° C.Therefore, the application temperature range is up to 500° C. unlessanother Schottky contact technique is used. Tungsten gate is onepossible candidate.

In FIG. 7, the effect of different post-gate RTA's on the fluorineatoms' distributions in AlGaN/GaN heterostructures, as measured by SIMSis shown. The untreated device is used as a reference.

It was found that the fluorine ions, which were incorporated into theAlGaN barrier layer by CF₄ plasma treatment, could effectively shift thethreshold voltage positively. The fluorine ions' incorporation in theAlGaN layer was confirmed by secondary-ion-mass-spectrum (SIMS)measurements, as shown in FIG. 7. During CF₄ plasma treatment, fluorineions are implanted into AlGaN/GaN heterostructure in a self-builtelectrical field stimulated by the RF power.

It is also concluded from the results shown in FIG. 7 that the implantedfluorine ions have a good thermal stability in the AlGaN layer up to700° C. Deep-level transient spectroscopy (“DLTS”) has been conducted onthe HEMT samples treated by CF₄ plasma. The fluorine ions incorporatedin the AlGaN barrier appear to introduce a deep-level state that is atleast 1.8 eV below the conduction-band minimum. As a result, thefluorine ions are believed to introduce a negatively chargedacceptor-like deep level in the AlGaN.

Recent DLTS and photo-conductivity results have revealed that theincorporation of fluorine ions in the AlGaN layer is predominantlysubstitutional, with the fluorine atoms filling nitrogen vacancies inthe AlGaN layer.

Note that in SIMS plots such as FIG. 7, it is difficult to make accuratecalculation of concentration from SIMS measurement because the beam sizeis not known. However, based on the bandstructure and threshold voltagecalculation, the peak value of the F concentration can be as high asabout 1×20 cm⁻³.

In FIG. 7A, the effect of different plasma power levels without RTA onthe fluorine atoms' distributions in AlGaN/GaN heterostructures, asmeasured by SIMS, is shown.

Note that the 200 W and 400 W lines show a “bump” at the interfacebetween the AlGaN/GaN interface. During an incorporation process, thefluorine ions can fill up surface or interface states (or “traps”)producing “anomalous stopping”. Therefore, this indicates there are moretraps at the interface. Further, the 600 W and 800 W lines do not showthe bump most likely because of the greater penetration depth andoverall concentration.

The untreated device is used as a reference. In FIG. 7B, the effect ofdifferent post-gate treatment temperatures at a fixed power of 600 W forRTA on the fluorine atoms' distributions in AlGaN/GaN heterostructures,as measured by SIMS, is shown. The untreated device is used as areference. Note that the distributions in the AlGaN for 700° C. andbelow show a normal effect of root Dt, but the distribution in the AlGaNlayer seems to reflect a very different diffusivity (or perhaps someother activation energy effect). Thus, the data indicates that fluorineions are more stable in AlGaN than in GaN. Further, the binding energycan be higher, and the fluorine-related energy states are deeper belowthe conduction band in AlGaN than in GaN.

Sensitivity to plasma treatment parameters was also investigated.Devices were fabricated with different V_(th) values by applyingdifferent CF₄ plasma power and treatment times. Five differentcombinations were used: 100 W for 60 seconds, 150 W for 20 seconds, 150W for 60 seconds, 150 W for 150 seconds, and 200 W for 60 seconds. Forcomparison, an HEMT without CF₄ treatment was also fabricated on thesame sample and in the same processing run. All the devices wereunpassivated in order to avoid any confusion caused by the passivationlayer, which may change the stress in the AlGaN layer and alter thepiezoelectric polarization. All the HEMT devices have a gate length of 1μm, a source-gate spacing of L_(sg)=1 μm and a gate-drain spacing ofL_(gd)=2 μm. DC current-voltage (I-V) characteristics of the fabricateddevices were measured using an HP4156A parameter analyzer. Transfercharacteristics and transconductance (g_(m)) characteristics are shownin FIGS. 8A and 8B, respectively. Taking the conventional HEMT (i.e.,without CF₄ plasma treatment) as the baseline devices, the thresholdvoltage of all the other CF₄ plasma-treated HEMTs are shifted to thepositive direction. Defining V_(th) as the gate-bias intercept of thelinear extrapolation of the drain-current at the point of peaktransconductance (g_(m)), the V_(th) of all the devices were extractedand listed in FIG. 9. For the conventional HEMT, V_(th) is −4 V. For theHEMT treated by CF₄ plasma at 150 W for 150 seconds, the V_(th) is 0.9V, which corresponds to the E-mode HEMT. A maximum V_(th) shift of 4.9 Vwas achieved. In order to further reveal the effects of CF₄ plasmatreatment, the dependencies of V_(th) on both CF₄ plasma treatment timeand RF power are plotted in FIG. 10. As the plasma power is increasedand as longer treatment time are utilized, larger shifts in V_(th) areeffected. With the increase in the plasma treatment time, more fluorineions were implated into AlGaN layer. The increased fluorine ionconcentration leads to a reduced electron density in the channel, andcauses the positive shift of V_(th). When the plasma power increases,fluorine ions obtain a higher energy and fluorine ion flux increases dueto the enhanced ionization rate of CF₄. With higher energy, fluorineions can reach at a deeper depth closer to the channel. The closer thefluorine ions are to the channel, the more effective they at depleting2DEG, and a larger shaft in V_(th) is achieved. The increased fluorineions flux has the same effect on V_(th) as the increase of the plasmatreatment time by raising the fluorine atoms concentration in AlGaNlayer. It should be noted that the nearly linear V_(th) versus time andV_(th) versus power relationships imply the possibilities of a precisecontrol of V_(th) of AlGaN/GaN HEMTs. Although the V_(th) is shifted byCF₄ plasma treatment, the g_(m) is not degraded. As shown in FIG. 8B,all the devices' maximum g_(m) are in the range of 149-166 mS/mm, exceptfor that treated at 150 W for 60 seconds, which has a higher peak g_(m)of 186 mS/mm. It is suspected that this singularity point was caused bythe non-uniformity in epitaxial growth. Confirmed by an AFM measurementconducted on a CF₄-treated patterned sample (with part of the sampletreated and other parts protected from the plasma treatment), the CF₄plasma treatment only results in an AlGaN-thickness reduction of lessthan 1 μm, as shown in FIG. 11. Thus, the almost constanttransconductance indicates that the 2DEG mobility in the channel ismaintained in the device fabrication according to the presentinnovations. A key step in maintaining the transconductance is thepost-gate annealing process.

Recovery of Plasma-Induced Damages by Post-Gate Annealing

As previously discussed, the plasma normally induces damages and createsdefects in semiconductor materials, and consequently degrades carriers'mobility. RTA is an effective method to repair these damages and recoverthe mobility. In the CF₄ plasma-treated AlGaN/GaN HEMTs, drain-currentand transconductance degradation occurs just after the plasma treatment.In FIGS. 12A and 12B, the drain-current and transconductance measured onan untreated device and a treated device (200 W, 60 seconds) before andafter RTA (400° C. for 10 minutes) are plotted. FIG. 13 compares theoutput characteristics of the treated device before and after RTA. Thedrain-current was 76% and the transconductance was 51% higher after theRTA in the treated device. The RTA process can recover majority of themobility degradation in the plasma-treated device while showing aninsignificant effect on the conventional untreated device. Therefore,the recovery of I_(d) and g_(m) in the CF₄ plasma-treated device is theresult of the effective recovery of the 2DEG mobility at this RTAcondition. Compared to a higher annealing temperature of 700° C., whichis needed to recover damages induced by chlorine-based ICP-RIE in thecase of recessed gate, this lower RTA temperature implies that the CF₄plasma treatment creates lower damages than the chlorine-based ICP-RIE.It also enables the RTA process to be carried out after the gatedeposition, fulfilling the goal of a self-aligned process. If theprevious definition of V_(th) is used, the V_(th) of the CF₄plasma-treated device seems to be shifted from 0.03 to −0.29 V after theRTA. When the start point of g_(m), as shown in FIG. 12B, or the startpoint of I_(d) at the logarithm scale, as shown in the inset of FIG.12A, is used as the criteria to evaluate V_(th), the V_(th) of the CF₄plasma-treated device is not changed after the RTA. The good thermalstability of V_(th) is consistent with the previously mentioned goodthermal stability of fluorine atoms in AlGaN layer.

Suppression of Schottky Gate-Leakage Current

AlGaN/GaN HEMTs always show much higher reverse gate leakage currentsthan the values theoretically predicted by the thermionic-emission(“TE”) model. The higher gate currents degrade the device's noiseperformance and raise the standby power consumption. In particular,forward gate currents limit the gate input voltage swing, hence themaximum drain-current. Other approaches have been attempted to suppressgate currents of AlGaN/GaN HEMTs. These efforts include using the gatemetal with higher work function, using copper, modifying the HEMTsstructure (such as adding a GaN cap), or diversion tometal-insulator-semiconductor heterostructure field-effect transistors(MISHFETs). In the CF₄ plasma-treated AlGaN/GaN HEMTs of the presentinnovations, suppressions of gate currents in both reverse and forwardbias regions can be achieved. Gate-current suppressions showdependencies on CF₄ plasma-treatment conditions.

FIGS. 14A and 14B shows gate currents of AlGaN/GaN HEMTs with differentCF₄ plasma treatments. FIG. 14B is the enlarged plot of the forward gatebias region. In reverse bias region, compared to the conventional HEMTwithout CF₄ plasma treatment, the gate-leakage currents of all the CF₄plasma-treated AlGaN/GaN HEMTs decreased. At V_(g)=−20 V, thegate-leakage current drops by more than four orders of magnitude from1.2×10⁻² A/mm for conventional HEMT to 7×10⁻⁷ A/mm for the AlGaN/GaNHEMT plasma treated at 200 W, 60 seconds. In the forward region, thegate currents of all the CF₄ plasma-treated AlGaN/GaN HEMTs alsodecrease. As a result, the turn-on voltages of the gate Schottky diodeare extended, and the gate input voltage swings are increased. Using 1mA/mm as the criterion, the turn-on voltage of the gate Schottky diodeincreases from 1 V for conventional HEMT to 1.75 V for the CF₄plasma-treated AlGaN/GaN HEMT at 200 W for 60 seconds.

The suppression of the gate-leakage current in the CF₄ plasma-treatedAlGaN/GaN HEMT can be explained as follows. During CF₄ plasma treatment,fluorine ions are incorporated into the AlGaN layer. These ions with astrong electronegativity act as immobile negative charges that cause theupward conduction-band bending in the AlGaN barrier layer due to theelectrostatic induction effect. Thus, an additional barrier heightΦ_(F), as shown in FIG. 23 is formed, and the effectivemetal-semiconductor barrier height is increased from Φ_(B) toΦ_(B)+Φ_(F). This enhanced barrier height can effectively suppress thegate Schottky diode current in both reverse and forward bias regions.With higher plasma power and longer treatment time, the fluorine ionconcentration in the AlGaN layer increases, and the effective barrierheight is raised further, leading to a more significant gate-currentsuppression. In FIG. 9 the effective barrier heights and idealityfactors that were extracted from the forward region of the measured gatecurrents by using the TE model are detailed. The effective barrierheight of conventional HEMT is 0.4 eV, while the effective barrierheight increases to 0.9 eV for the CF₄ plasma-treated HEMT at 200 W for60 seconds. The effective barrier heights of the CF₄ plasma-treated HEMTalso show a trend of increase with the plasma power and treatment time,except for the HEMT treated at 150 W for 20 seconds, which has arelatively higher effective barrier height. This exception is thought tobe due to the process variations. The facts that the extracted effectivebarrier height is much lower than the theoretically predicted values andvery large ideality factors (>2.4) indicates that the gate currents offabricated AlGaN/GaN HEMTs are not dominated by the TE mechanism butother mechanisms, such as vertical tunneling, surface barrier thinning,and trap-assisted tunneling. Thus, the barrier heights can idealityfactors, which are extracted by using the TE model, are not accurate.Nevertheless, they provide sufficient qualitative information forexplaining the mechanism of the gate-current suppression in CF₄plasma-treated AlGaN/GaN HEMTs.

Dynamic I-V characterizations were conducted by using all Accent DIVAD265 system to investigate the effects of CF₄ plasma treatment ondrain-current dispersion. The pulse width is 0.2 μs and the pulseseparation is 1 ms. The quiescent point is at V_(GS) slightly (˜0.5 V)below the pinch-off and V_(DS)=15 V. Compared to static I-Vcharacteristics, the maximum drain-current of conventional D-mode HEMTdropped by 63%, while that of E-mode HEMT with CF₄ plasma treatment at150 W for 150 seconds dropped by 6%.

The alleviation of drain-current drops for E-mode HEMT is likely due toa raised gate bias of the quiescent point (V_(GS)=0 V for E-mode HEMT,V_(GS)=−4.5 V for D-mode HEMT).

RF Small-Signal Characteristics

On-wafer small-signal RF characterization of the fabricated AlGaN/GaNHEMTs were carried out at the frequency range of 0.1-39.1 GHz usingCascade microwave probes and an Agilent 8722ES network analyzer.Open-pad de-embeddings with the S-parameters of dummy pads were carriedout to eliminate a parasitic capacitance of the probing pads. Thecurrent gain and maximum stable gain/maximum available gain (MSG/MAG) ofall devices with 1-μm long gate were derived from the de-embeddedS-parameters as a function of frequency. The current cutoff frequency(f_(t)) and maximum oscillation frequency (f_(max)) were extracted fromcurrent gains and MSG/MAGs at unit gain. It has been observed that theintrinsic f_(t) and f_(max) are generally 10-15% higher than theextrinsic ones without the de-embeddings process. The dependencies off_(t) and f_(max) on the gate bias are shown in FIG. 15 for the E-modeHEMT. Both f_(t) and f_(max) are relatively constant at both low andhigh gate bias, indicating a good linearity. FIG. 16 lists f_(t) andf_(max) of all samples. For the conventional HEMT, f_(t) and f_(max) are13.1 and 37.1 GHz, while for the CF₄ plasma-treated HEMT, f_(t) andf_(max) are approximately 10 and 34 GHz, slightly lower than that of theconventional HEMT, except for the HEMT treated at 150 W for 60 seconds.This higher f_(t) and f_(max) in the 150 W/60 second device are constantwith the higher g_(m) presented before, and are attributed to a materialnon-uniformity and process variation. The slightly lower f_(t) andf_(max) in the CF₄ plasma-treated HEMTs indicate that the post-gate RTAat 400° C. can effectively recover the 2DEG mobility degraded by theplasma treatment, but the recovery is less than 100%. It suggests thatthe optimization of the RTA temperature and time is needed to furtherimprove the 2DEG mobility, while not degrading the gate Schottkycontact.

MISHFETs

In another embodiment, E-mode Si₃N₄/AlGaN/GaN MISHFET were constructedwith a two-step Si₃N₄ process which features a thin layer of Si₃N₄ (15nm) under the gate and a thick layer of Si₃N₄ (about 125 nm) in theaccess region. Fluorine-based plasma treatment was used to convert thedevice from D-mode to E-mode. The E-mode MISHFETs with 1-μm long gatefootprint exhibited a threshold voltage of 2 V, a forward turn-on gatebias of 6.8 V (compared to about a 3 V realized in E-mode AlGaN/GaNHEMTs) and a maximum current density of 420 mA/mm.

The AlGaN/GaN HFET structure was used in this example was grown on(0001) sapphire substrates in an Aixtron AIX 2000 HT MOCVD system. TheHFET structure consists of a 50-nm thick low temperature GaN nucleationlayer, a 2.5-μm thick not-intentionally doped GaN buffer layer, and anAlGaN barrier layer with nominal 30% Al composition. The barrier layeris composed of a 3-nm undoped spacer, a 16-nm carrier supplier layerdoped at 2×10¹⁸ cm⁻³, and a 2-nm undoped cap layer. Thecapacitance-voltage (“C-V”) measurement by mercury probe yields aninitial threshold voltage of −4 V for this sample. The process flow isillustrated in FIGS. 17A through 17F. The device mesa is formed usingCl₂/He plasma dry etching in an STS ICP-RIE system followed by thesource/drain ohmic contact information with Ti/Al/Ni/Au (20 nm/150 nm/50nm/80 nm) annealed at 850° C. for 30 seconds, as shown in FIG. 17A.Then, the first Si₃N₄ layer (about 125 nm) is deposited on the sample byplasma enhanced chemical vapor deposition (PECVD) as in FIG. 17B. Aftergate windows with 1-μm length are opened by photolithography, the samplewas put in an RIE system under CF₄ plasma treatment, which removed theSi₃N₄ and incorporated fluorine ions in the AlGaN. The RF power of theplasma was 150 W, as shown in FIG. 17C. The gas flow was controlled tobe 150 sccm, and the total etching and treatment time is 190 seconds.After removing the photoresist, the second Si₃N₄ film (about 15 nm) wasdeposited by PECVD to form the insulating layer between gate metal andAlGaN as in FIG. 17D. Subsequently, the Si₃N₄ layer was patterned andetched to open windows in the source and drain ohmic contact regions, asshown in FIG. 17E. Next, the 2-μm long gate electrodes were defined byphotolithography followed by e-beam evaporation of Ni/Au (˜50 nm/300 nm)and liftoff as in FIG. 17F. To ensure that the gate electrode covers theentire plasma-treated region, the metal gate length (2 μm) was chosen tobe larger than the treated gate area (1 μm), leading to a T-gateconfiguration. The gate overhang in the source/drain access regions isinsulated from the AlGaN layer by the thick Si₃N₄ layer, keeping thegate capacitances at low level. Finally, the whole sample was annealedat 400° C. for 10 minutes to repair the plasma-induced damage in theAlGaN barrier and channel. Measured from the foot of gate, thegate-source and gate-drain spacings are both 1.5 μm. The E-mode MISHFETsare designed with gate width of 10 μm for dc testing and 100 μm for RFcharacterizations.

The constructed device was then characterized. The DC outputcharacteristics of the E-mode MISHFETs are plotted in FIG. 18. Thedevices exhibit a peak current density of about 420 mA/mm, anON-resistance of about 5.67 Ω·mm and a knee voltage of about 3.3 V atV_(GS)=7 V. FIG. 19A shows the transfer characteristics of the samedevice with 1×10-μm gate dimension. It can be seen that the V_(th) isabout 2 V, indicating a 6-V shift of V_(th) (compared to a conventionalD-mode HFET) achieved by the insertion of the Si₃N₄ insulator and plasmatreatment. The peak transconductance gm is about 125 mS/mm. FIG. 19Bshows the gate leakage current at both the negative bias and forwardbias. The forward bias turn-on voltage for the gate is about 6.8 V,providing a much larger gate bias swing compared to the E-mode HFETs.Pulse measurements were taken on the E-mode MISHFETs with 1×100-μm gatedimensions with a pulse length of 0.2 μs and a pulse separation of 1 ms.The quiescent bias point is chosen at V_(GS)=0 V (below V_(th)) andV_(DS)=20 V. FIG. 20 shows that the pulsed peak current is higher thanthe static one, indicating no current collapse in the device. The staticmaximum current density of the large device with the a 100-μm gate widthis about 330 mA/mm, smaller than the device with 10-μm gate width (about420 mA/mm). The lower peak current density in the larger device is dueto the self-heating effect that lowers the current density. Since littleself-heating occurs during pulse measurements, the maximum current forthe 100-μm wide device can reach the same level as the 10-μm widedevice. On wafer small-signal RF characteristics were performed from 0.1to 39.1 GHz on the 100-μm wide E-mode MISHFETs at V_(DS)=10 V. As shownin FIG. 21, the maximum current gain cutoff frequency (f_(T)) and powergain cutoff frequency (f_(max)) are 13.3 and 23.3 GHz, respectively.When the gate bias is 7 V, the small-signal RF performance does notsignificantly degrade, with an f_(T) of 13.1 GHz and an f_(max) of 20.7GHz, indicating that the Si₃N₄ insulator offers an excellent insulationbetween gate metal and semiconductor.

Models

A theoretical characterization model was developed for some of thepresent innovations. For a conventional AlGaN/GaN HEMT with siliconmodulation doped layer, as shown in FIG. 7, the polarization charge needto be taken into account in the calculation of HEMTs threshold voltage.Modified from a generally used formula by taking into account theeffects of charge polarization, surface and buffer traps, the thresholdvoltage of the AlGaN/GaN HEMT can be expressed as:

$\begin{matrix}{V_{th} = {{\phi_{B}/e} - {d\;{\sigma/ɛ}} - {\Delta\;{E_{C}/e}} + {E_{f\; 0}/e} - {\frac{e}{ɛ}{\int_{0}^{d}{{\mathbb{d}x}{\int_{0}^{x}{{N_{si}(x)}{\mathbb{d}x}}}}}} - {e\;{{dN}_{st}/ɛ}} - {e\;{N_{b}/{C_{b}.}}}}} & (1)\end{matrix}$Where the parameters are defined as follows:

φ_(B) is the metal-semiconductor Schottky barrier height.

σ is the overall net (both spontaneous and piezoelectric) polarizationcharge at the barrier—AlGaN GaN interface.

d is the AlGaN barrier-layer thickness.

N_(si)(x) is the silicon-doping concentration.

ΔE_(c) is the conduction-band offset at the AlGaN/GaN heterostructure.

E_(f0) is the difference between the intrinsic Fermi level and theconduction band edge of the GaN channel.

ε is the dielectric constant of AlGaN.

N_(st) is the net-charged surface traps per unit area.

N_(b) is the effective net-charged buffer traps per unit area.

C_(b) is the effective buffer-to-channel capacitance per unit area.

The last two terms in equation (1) describe the effects of the surfacetraps and buffer traps, respectively. The AlGaN surface is at x=0, andthe direction pointing to the channel is the positive direction for theintegration. To represent the devices described above, immobile negativecharges are introduced into the AlGaN barrier layer under the gate.Because of electrostatic induction, these immobile negative charges candeplete 2DEG in the channel, raise the energy band, and hence modulateV_(th). Including the effect of the negative charges confined in theAlGaN barrier, the modified threshold voltage from equation (1) is givenby:

$\begin{matrix}{V_{th} = {{\phi_{B}/e} - {d\;{\sigma/ɛ}} - {\Delta\;{E_{C}/e}} + {E_{f\; 0}/e} - {\frac{e}{ɛ}{\int_{0}^{d}{{\mathbb{d}x}{\int_{0}^{x}{\left( {{N_{si}(x)} - {N_{F}(x)}} \right){\mathbb{d}x}}}}}} - {e\;{{dN}_{st}^{\prime}/ɛ}} - {e\;{N_{b}/{C_{b}.}}}}} & (2)\end{matrix}$The positive-charge distribution profile N_(si)(x) is replaced by thenet charge distribution N_(si)(x)−N_(F)(x), where N_(F)(x) is theconcentration of the negatively charged fluorine ion. The surface-trapdensity (N_(st)) could be modified by the plasma treatment.

By applying Poisson's equation and Fermi-Dirac statistics, a simulationwas made of the conduction-band profiles and the electron distributionsof AlGaN/GaN HEMT structures with and without fluorine ions incorporatedin AlGaN layer. Both structures have the same epitaxial structure, shownin FIG. 7. For the fluorine ions incorporated HEMT structure, thenegatively charged fluorine ions' profile was extracted from SIMSmeasurement results of the fluorine atoms' distribution of an AlGaN/GaNHEMT structure that was treated by CF₄ plasma at 150 W for 150 s andconverted to an E-mode HEMT. The simulated conduction band diagrams atzero gate bias were plotted in FIGS. 22 and 23 For the simulatedconduction band of E-mode HEMT, as shown in FIG. 22 the fluorineconcentration is approximated by using a linear distribution that thepeak fluorine concentration is 3×10¹⁹ cm⁻³ at the AlGaN surface, and thefluorine concentration is assumed to be negligible at the AlGaN/GaNinterface. A total fluorine ion sheet concentration of about 3×10¹³ cm⁻²is sufficient to not only compensate the silicon doping (about 3.7×10¹³cm⁻²) in the AlGaN barrier but also to compensate for the piezoelectricand spontaneous polarization-induced charges (about 1×10¹³ cm⁻²). Twosignificant features can be observed. First, compared to the untreatedAlGaN/GaN HEMT structure, the plasma-treated structure has its 2DEGchannel's conduction-band minimum above Fermi level, indicating acompletely depleted channel and E-mode HEMT. As shown in the electronprofiles in FIG. 24, there are no electrons in the channel under thezero gate bias in the plasma-treated structure, indicating an E-modeHEMT operation. Second, the immobile negatively charged fluorine ionscause an upward bending of the conduction band, especially in AlGaNbarrier, yielding an additional barrier height ΦF, as shown in FIG. 23Such an enhanced barrier can significantly suppress the gate Schottkydiode current of AlGaN/GaN HEMT in both the reverse and forward biasregion.

The epitaxial structure for the monolithically-integrated E/D-mode HFETconsists of: (a) a semiconductor substrate (sapphire, SiC, silicon, AlNor GaN, etc.); (b) a buffer layer grown on the substrate; (c) a channellayer ; (d) a barrier layer including an undoped spacer layer, amodulation doped carrier supply layer and an undoped cap layer. Thefabrication process includes: (f) active region isolation; (g) ohmiccontacts formation on source and drain terminals; (h) photolithographyof the gate regions for the E-mode HFETs; (i) fluoride-based plasmatreatment to the exposed barrier layer of the E-mode HFETs; (j) gatemetal deposition of the E-mode HFETs; (k) photolithography of the gateregions for the D-mode HFETs; (l) gate metal deposition of the D-modeHFETs; ml) surface passivation of the D-mode and E-mode HFETs; (n) gateannealing at elevated temperatures. A schematic process flow for thismonolithic integration is depicted in FIG. 25.

The active device isolation in the above-described monolithicintegration process uses the mesa etching, which features the activeregion removal by etching techniques in the areas without the HFETs.Such an approach imposes limits to the integration density,photolithography resolution . For high frequency circuits, the edges ofthe mesas also introduce additional discontinuities for wavepropagation, which in turn, complicate the circuit design and analysis.Since the fluoride-based plasma treatment is able to deplete theelectrons in the channel (providing electrical turn-off of the channel),it can be used for device isolation. With increased plasma power andtreatment time, the regions where active devices are not desired can becompletely turned off electrically, providing electrical isolationbetween devices. Such an approach does not involve any material removal,therefore, enables a flat wafer surface for planar process.

EXAMPLE

FIGS. 26A through 26F illustrate the process of monolithicallyintegrating the E/D-mode HFETs for integrated circuits according to oneembodiment of the present invention. FIG. 26A illustrates a preferredepitaxial structure of this invention, where the reference numerals 110,120, 130 and 140 denote substrate, low temperature grown GaN nucleationlayer, high temperature grown GaN buffer layer, and Al_(x)Ga_(1-x)Nbarrier layer including the modulation doped carrier supply layer. Themanufacturing method of monolithic integration of E/D-mode HFETs forintegrated circuits is described below. For both D-mode and E-modeHFETs, the mesa isolations are simultaneously formed, using Cl2/Heplasma dry etching followed by the source/drain ohmic contact formation160 with Ti, Al, Ni and Au annealed at 850° C. for 45 seconds as shownin FIG. 26B. The gates as well as gate-source interconnections of D-modeHFETs are patterned by photoresist 170 as shown in FIG. 26C, followed bydepositing and lift-off Ni and Au 178. Thereafter, the E-mode HFETs'gates, pads and second interconnections are patterned with photoresist175 as shown in FIG. 26D. Then the fluoride ions are incorporated intoAl_(x)Ga_(1-x)N barrier layer beneath E-mode HFETs' gates by, forexamples, either fluoride plasma treatment or fluoride ions implantationas shown in FIG. 26D. The gate electrode 180 is formed on the barrierlayer 140 by depositing and lift-off Ni and Au. Thereafter, post-gaterapid thermal annealing (RTA) is conducted at 400-450° C. for 10minutes. A passivation layer 190 is grown on the top of the wafer asshown in FIG. 26E. Then the contact pads and via holes are opened byremoving portions of the passivation layer on them as shown in FIG. 26F.Finally, a third interconnection is formed.

An E/D HFETs inverter and a 17-stage direct-coupled ring oscillator werecreated on a 20 nm Al_(0.25)Ga_(0.75)N barrier layer on 2 μm GaN bufferlayer with typical CF₄ plasma treatment condition of 150 W for 150seconds and typical post-gate RTA condition of 450° C. for 10 minutesfor E-mode HFETs. The inverter has a NM_(L) of 0.21 V and a NM_(H) of0.51V at a supply voltage of 1.5 V. When supply voltage of 3.5 V isapplied, the 17-stage ring oscillator shows a maximum oscillationfrequency of 225 MHz corresponding to a minimum propagation delay of 130ps.

EXAMPLE

This embodiment describes a method for planar monolithic integration ofE-mode and D-mode AlGaN/GaN HFETs. As described in the first embodiment,the isolation among active devices can be obtained by creating activedevice mesa through etching, which creates a non-flat wafer surfaces. Inintegrated circuit fabrications, planar process are always desirable.Following the same principle of channel depletion by the negativelycharged fluorine ions in the AlGaN, depletion of the desired inactive(isolated) areas by fluoride-based plasma treatment can be effected. Theplasma power and treatment time can both be increased to enhance thecarrier depletion. The process flow is illustrated in FIG. 27, where:(a) source/drain ohmic contacts formation; (b) D-mode HFET gatedefinition by photolithography; (c) D-mode HFET gate metallization andpart of the interconnects formation; (d) E-mode HFET gate definition byphotolithography followed by plasma treatment; (e) E-mode HFET gatemetallization and part of the interconnects formation; (f) isolationregion definition by photolithography followed by the secondfluoride-based plasma treatment; (g) final chip followed by passivation.

EXAMPLE

The AlGaN/GaN HEMT structure in this example was grown on a (0001)sapphire substrates in an Aixtron AIX 2000 HT MOCVD system. The HEMTstructure consists of a low-temperature GaN nucleation layer, a 2.5-μmthick unintentionally doped GaN buffer layer, and an AlGaN barrier layerwith a nominal 30% Al composition. The barrier layer is composed of a3-nm undoped spacer, a 21-nm carrier supplied layer doped at 2×1018cm⁻³, and a 2-nm undoped cap layer. Room-temperature hall measurementsof the structure yield an electron sheet density of 1.3×1013 cm⁻² and anelectron mobility of 950 cm²/Vs.

The integration process flow is illustrated in FIG. 28. First, thesource/drain ohmic contacts of the E/D-mode devices were formedsimultaneously by a deposition of e-beam evaporated Ti/Al/Ni/Au (20nm/150 nm/50 nm/80 nm) and rapid thermal annealing at 850° C. for 30seconds, as shown in FIG. 28( a). Second, the active regions for bothE/D-mode devices were patterned by a photolithography, which is followedby the CF₄ plasma treatment in a reactive ion etching system. The plasmapower was 300 W, and the treatment time was 100 seconds. The gas flowwas controlled to be 150 sccm, and the plasma bias was set to be 0 V.The isolation regions are the locations where a large amount of fluorineions are incorporated in the AlGaN and GaN layers near the surface, andthen deplete the two-dimensional electron gas in the channel, as shownin FIG. 28( b). The D-mode HEMTs' gate electrodes were then patterned bythe contact photolithography, which is followed by the e-beamevaporation of Ni/Au (50 nm/300 nm) and liftoff as shown in FIG. 28( c).Next, E-mode HEMTs' gate electrodes and interconnections were defined.Prior to the e-beam evaporation of Ni/Au, the gate regions of the E-modeHEMTs were treated by the CF₄ plasma (which has a negligible etching toAlGaN) at 170 W for 150 seconds, as shown in FIG. 28( d). This plasmatreatment performed the function of converting the treated devices fromthe D-mode to E-mode HEMT. A 200-nm-thick silicon nitride passivationlayer was deposited by PECVD, and the probing pads were opened. Then,the sample was annealed at 400° C. for 10 minutes to repair theplasma-induced damage in the AlGaN barrier and channel of the E-modeHEMTs as in FIG. 28( e). As a comparison, the D-mode devices werefabricated on another piece of the sample from the same substrate by thestandard process, in which inductively coupled plasma reactive ionetching was used to define the mesa as the active region. For thedirect-coupled FET logic inverter shown in FIG. 1A, the E-mode HEMTdriver is designed with a gate length, gate-source spacing, gate-drainspacing, and gate width of 1.5, 1.5, 1.5, and 50 μm, respectively; theD-mode HEMT load is designed with a gate length, gate-source spacing,gate-drain spacing, and gate width of 4, 3, 3, and 8 μm, yielding aratio β=(W_(E)/L_(E))/(W_(D)/L_(D)) of 16.7. Discrete E-mode and D-modeHEMTs with 1.5×100 μm gate dimension are fabricated forcharacterizations.

Device and Circuit Characteristics

For the E/D-mode HEMTs fabricated by the planar process, the outputcharacteristics are plotted in FIG. 29. The peak current density forD-mode and E-mode HEMTs are about 730 and 190 mA/mm. FIG. 30 shows theDC transfer characteristics comparison between the planar and thestandard process. It can be seen that the drain leakage current for theplanar process is about 0.3 mA/mm, reaching the same level as thedevices fabricated by the standard mesa etching. The D-mode HEMTs by theplanar process have the comparable drain-current and transconductancecharacteristics as shown in FIG. 30( b), as the ones by the standardprocess. Also, the leakage current between two pads (400×100 μm²) wasmeasured with a spacing of 150 μm. At the DC bias of 10 V, the leakagecurrent by the planar process is about 38 μA, at the same level of thestandard mesa etching sample (about 30 μA). Compared with the standardmesa process, the fluoride-based plasma treatment can achieve the samelevel of the active device isolation, enabling a completeplanar-integration process. The E-mode HEMTs exhibit a smallertransconductance (“g_(m)”) compared to the D-mode devices, which is dueto the incomplete recovery of the plasma-induced damage. The fact thatthe sample has been through a thermal annealing at 400° C. alsoindicates that a good thermal stability is expected at a temperature atleast up to 400° C. It should be noted that an ion-implantationtechnique has also been developed for inter-device isolationaccomplished by a multiple energy N+ implantation to produce significantlattice damage throughout the thickness of the GaN buffer layer.Compared to the ion-implantation technique, the CF₄ plasma-treatmenttechnique has the advantages of low cost and low damage.

The E/D-mode HEMTs DCFL inverter fabricated by the planar-integrationprocess was characterized. FIG. 31 shows the measured static voltagetransfer curve of the inverter at a supply voltage V_(DD)=3.3 V. High-and low-output logic levels (V_(OH) and V_(OL)) are 3.3 and 0.45 V,respectively, with the output swing (V_(OH)-V_(OL)) of 2.85 V. The DCvoltage gain in the linear region is 2.9. By defining the values ofV_(IL) and V_(IH) at the unit gain points, the low and high noisemargins are 0.34 and 1.47 V. The inverter DC circuit is also shown inFIG. 31. The leakage current with the E-mode device pinch-off is about 3μA, which is consistent with the discrete device results.

EXAMPLE

FIG. 32 shows AlGaN/GaN epitaxial heterostructures during thefabrication of an HEMTs according to the present innovations. Theyinclude the following: 2.5 μm GaN buffer layer and channel, 2 nm undopedAl_(0.25)Ga0_(.75)N spacer, 15 nm Al_(0.25)Ga_(0.75)N carrier supplylayer with Si doping at 1×1018 cm⁻³, and a 3 nm undopedAl_(0.25)Ga_(0.75)N cap layer. The structures were grown on sapphiresubstrate in an Aixtron 2000 HT MOCVD system. The process flow is shownin FIGS. 33( a) through 33(f).

The mesa and source/drain ohmic contacts were formed simultaneously forboth E-mode and D-mode HEMTs, as shown in FIG. 33( a) and (b). TheD-mode HEMTs' gate electrodes were then formed by photolithography,metal deposition, and liftoff, as shown in FIGS. 33( c) and (d). Afterdefining the patterns of E-mode HEMTs' gates and interconnections,samples were treated by CF₄ plasma at a source power of 150 W for 150seconds in an STS RIE system as shown in FIG. 33( e), followed by gatemetallization and lift-off for the E-mode HEMTs. Inspected by atomicforce microscope (“AFM”) measurements, the AlGaN barrier thickness wasreduced by 0.8 nm after the plasma treatment. Next, a post-gate thermalannealing was conducted at 450° C. for 10 minutes as shown in FIG. 33(f). The CF₄ plasma treatment converts the treated GaN HEMT from D-modeto E-mode. The magnitude of threshold voltage shift depends on thetreatment conditions, e.g., plasma power and treatment time, asdescribed previously. The post-gate annealing is employed to recover theplasma-induced damages in AlGaN barrier and channel. In principle, thehigher is the annealing temperature, the more efficient is the damagerepair. However, in practice, the post-gate annealing temperature shouldnot exceed the highest temperature (˜500° C., in our case) that the gateSchottky contact can endure, as mentioned earlier. It was found that theD-mode HEMTs' characteristics remain the same after the annealing ,whereas the E-mode HEMTs' drain current density increases significantly.The post-gate annealing was found to have no effect on the thresholdvoltage shift introduced by the plasma treatment.

For the E/D inverter and the ring oscillator, the most importantphysical design parameter is the drive/load ratio,β=(W_(g)/L_(g))E-mode/(W_(g)/L_(g))D-mode. Several E/D inverters andring oscillators with β varying from 6.7 to 50 were designed andfabricated on the same sample. The geometric parameters of each designare listed in FIG. 34. Discrete E-mode and D-mode GaN HEMTs with 1×100μm gate dimension were simultaneously fabricated on the same sample fordc and RF testing.

Characteristics of E/D-mode HEMTs

DC current-voltage (I-V) characteristics of the discrete devices weremeasured using an HP4156A parameter analyzer. The transfercharacteristics of the E/D-mode HEMTs are plotted in FIG. 35( a).On-wafer small-signal RF characterization of the discrete devices werecarried out in the frequency range of 0.1-39.1 GHz using Cascademicrowave probes and an Agilent 8722ES network analyzer. The measuredparameters of E/D-mode HEMTs are listed in FIG. 36. The thresholdvoltage and peak transconductance (g_(m,max)) are 0.75 V and 132 mS/mmfor the E-mode HEMT and −2.6 V and 142 mS/mm for the D-mode HEMT. Therelatively low peak current density of 480 mA/mm for D-mode HEMT is dueto relatively low Al composition of 25% and relatively low dopingdensity of 1×1018 cm⁻³ in AlGaN barrier layer. Different from theAlGaN/GaN HEMTs used for RF/microwave power amplifiers, the digital ICsare less demanding on the current density. As shown in FIG. 35( b), alow knee voltage of 2.5 V is obtained for E-mode HEMTs. At a gate biasof 2.5 V, an on-resistance of 7.1 Ω·mm was achieved for the E-mode HEMT,which is the same as that for the D-mode HEMT at the same saturationcurrent level. One observation is that the gate current in both thereverse- and forward-bias conditions is significantly reduced in theE-mode HEMT as shown in FIG. 37( a) compared to the D-mode HEMT. Themechanism of this gate current suppression is the modulation of thepotential in the AlGaN barrier by the negatively charged fluorine ionsthat are introduced by the plasma treatment. The conduction-edge banddiagrams simulated for both D- and E-mode HEMTs by solving Poisson'sequation and Fermi-Dirac statistics. For the simulated conduction bandof E-mode HEMTs, the profile of fluorine distribution is approximated bya linear function that features a maximum fluorine ion concentration of3×1019 cm⁻³ at the AlGaN surface and reaches zero (negligible) at theAlGaN/GaN interface. A total fluorine ion sheet concentration of about3×1013 cm⁻² is sufficient to compensate no only the Si+ donors'concentration of about 3.7×1012 cm⁻² but also the piezoelectric andspontaneous polarization-induced charges (about 1×1013 cm⁻²). It shouldbe noted that the Schottky barrier height at the gate/AlGaN junction isassumed to remain the same in this example. As seen from the simulatedconduction bands shown in FIG. 37( b) and (c), the potential of theAlGaN barrier can be significantly enhanced by the incorporation of thefluorine ions, resulting in enhanced Schottky barrier and the subsequentgate current suppression. The gate current suppression in the forwardbias is particularly beneficial to digital IC applications. Thesuppressed gate current allows the E-mode devices' gate bias to beincreased up to 2.5 V. Such an increase results in a larger gate voltageswing, larger dynamic range for the input, and higher fan-out. Theincreased input voltage swing permits higher supply voltage that is animportant factor in achieving higher operation speed and higher noisemargins for digital ICs. Without the increased gate input swing, alarger supply voltage will lead to an output voltage (at logic “high”)that exceeds the turn-on voltage of the following stage's input gate.The wider dynamic range for the input enables direct logic levelmatching between the input and the output, eliminating the need forlevel adjustment between adjacent stages.

It should be noted that silicon nitride passivation, which is importanttechnique generally used for the stable operation of the GaN-basedHEMTs, can also affect the threshold voltage to a lesser degree. Thedeposition of silicon nitride passivation layer on the active region, ingeneral, can alter the stress in the AlGaN and GaN layers. Subsequently,the piezoelectric polarization charge density and the threshold voltageof the device can be slightly modified. In general, the widely usedsilicon nitride layer deposited by high-frequency PECVD introducesadditional tensile stress in the AlGaN layer, resulting in a negativeshift of the threshold voltage in the range of a few tenths of a volt.In practice, this effect should be taken into consideration in theprocess design. The plasma treatment dose can be increased accordinglyto compensate the negative shift in threshold voltage by the SiNpassivation layer. The stress of the SiN passivation layer can also bereduced by modifying the process parameters of the PECVD deposition sothat the negative shift in the threshold voltage is minimized.

EXAMPLE DCFL Inverter

The circuit schematic of an E/D HEMT inverter is shown in FIG. 1( a),where the D-mode HEMT is used as load with its gate tied to its sourceand the E-mode HEMT is used as a driver. FIG. 1B shows a fabricatedphotomicrograph of an inverter according to the present innovations. Thefabricated inverters were characterized using an HP4156A parameteranalyzer. FIG. 38 shows the static voltage transfer characteristics (thesolid curve) for a typical E/D HEMT inverter. The rise in the outputvoltage at the large input voltages (>2.1 V) is a result of the gateSchottky diode's turn-on. The dashed curve is the same transfer curvewith the axis interchanged and represents the input-outputcharacteristics of the next inverter stage. The parameter definitionsfollow those given for GaAs- and InP-based HEMTs. The static outputlevels (V_(OH) and V_(OL)) are given by the two intersections of thecurves in stable equilibrium points, and the difference between the twolevels is defined as the output logic voltage swing. The inverterthreshold voltage (V_(TH)) is defined as V_(in), where V_(in) is equalto V_(out). The static noise margins are measured using the method oflargest width for both logic-low noise margin (NM_(L)) and logic-highnoise margin (NM_(H)). The measured static voltage transfer curves ofE/D inverters with β varied from 6.7 to 50 at a supply voltageV_(DD)=1.5 V are plotted in FIG. 39. High output logic level (V_(OH)) ismaintained at 1.5 V, indicating that the E-mode HEMTs are well switchedoff, whereas low output logic level (V_(OL)) is improved from 0.34 to0.09 V as a result of β increasing from 6.7 to 50. As a result, theoutput logic swing defined as V_(OH)-V_(OL) increases from 1.16 to 1.41V. As β is increased from 6.7 to 50, V_(TH) decreases from 0.88 to 0.61V, the DC voltage gain (G) in the linear region increases from 2 to 4.1.FIG. 40 lists the measured values of static noise margins, as well asV_(OH), V_(OL), output logic swing, V_(TH), and G. Both NM_(L) andNM_(H) are improved as β increases.

The static voltage transfer curves of the inverter with β=10 weremeasured at different supply voltages and are plotted in FIG. 41. Thecircuit performance parameters are listed in FIG. 42. When supplyvoltage increases, all the parameters of E/D inverter increaseaccordingly. This means that the increase of supply voltage improves thestatic performance of the E/D invert. As well known, for HEMT and MESFETE/D inverters, the input voltage is always limited by the turn-onvoltage of the gate Schottky diode. At a large input voltage, gateconduction causes an increased voltage drop across the parasitic sourceresistance of the E-mode device that is used as a driver, raising thevoltage of the logic low level. The rise in the output voltage can beobserved in the static transfer curves as the supply voltage and therequired input voltage increase, as shown in FIG. 41. The gate current,when increased by the large input voltage, can significantly degrade theinverter's capability of driving multiple stages, reducing the fan-out.Usually, the turn-on voltage of the gate Schottky diode is around 1 Vfor a normal AlGaN/GaN HEMT. For a gate-recessed E-mode GaN HEMT, thethinned AlGaN barrier further decreases the turn-on voltage due to anenhanced tunneling current. As a result, for the inverter based on agate-recessed E-mode GaN HEMT, the output voltage rises when the inputvoltage is beyond 0.8 V. As disclosed earlier, the E-mode GaN HEMTfabricated by CF₄ plasma treatment possesses a suppressed gate currentbecause of the enhanced Schottky barrier in the AlGaN layer, which isinduced by the electronegative fluorine ions. Such a gate currentsuppression enables a larger input voltage swing for the E/D inverter.As can be seen in FIG. 41, the rise in output voltage does not occuruntil the input voltage is beyond 2 V, indicating about 1 V extension ofinput voltage swing. FIG. 43 shows the dependences of the load currentand input current on the input voltage. The lower input current (gatecurrent of the E-mode HEMT) implies a larger amount of fan-out. At “ON”state, the input current exceeds 10% load current when the input voltageis larger than 2 V.

EXAMPLE DCFL Ring Oscillator

FIG. 1B shows a schematic circuit diagram of a DCFL ring oscillator,which is formed with an odd-numbered E/D inverter chain. Seventeen-stagering oscillators were fabricated with inverters' β=6.7, 10, and 25. Foreach ring oscillator, 36 transistors were used including an outputbuffer. FIG 1D shows a photomicrograph of a fabricated ring oscillatoraccording to the present innovations. The ring oscillator werecharacterized on-wafer using an Agilent E4404B spectrum analyzer and anHP 54522A oscilloscope. The DC power consumption was also measuredduring the ring oscillators' operation. FIGS. 44 and 45 show thefrequency- and time-domain characteristics of the 17-stage ringoscillator with β=10 biased at V_(DD)=3.5 V. The fundamental oscillationfrequency is 225 MHz. According to the formula of propagation delay perstage τpd=(2nf)⁻¹, where the number of stages n is 17, and τ_(pd) wascalculated to be 130 ps/stage. The dependences of τ_(pd) and power-delayproduct on V_(DD) were plotted in FIG. 46. With the increase of supplyvoltage, the propagation delay was reduced, whereas power-delay productincreases. Compared to τ_(pd) (234 ps/stage) measured at 1 V, τ_(pd)measured at 3.5 V is reduced by 45%. The fact that the ring oscillatorcan operate at such a high V_(DD) attributes to the larger input voltageswing realized by the CF₄ plasma treatment technique used in theintegration process. A minimum power-delay product of 0.113 pJ/stage wasfound at a V_(DD) of 1 V. FIG. 46 also shows τ_(pd) and power-delayproduct characteristics of ring oscillators with β=6.7 and 25. For thering oscillator with β=6.7, the largest τ_(pd) and power-delay productis due to the larger input capacitance determined by the larger gatelength (1.5 μm) of the E-mode HEMT. For the ring oscillator with β=25,the larger τ_(pd) is due to the lower charging current determined by thelarger gate length (4 μm) of the D-mode HEMT, whereas the power-delayproduct is at the same level as the one with β=10. When this integrationtechnology is implemented in the sub-micrometer regime, the gate delaytime is expected to be further reduced.

Recently, the discrete E-mode HEMTs and the DCFL ring oscillators havebeen tested at elevated temperature up to 375 C. No significant shifthas been observed in the threshold voltage of the E-mode HEMTs, and thering oscillator exhibits an oscillation frequency of 70 MHz at 375 C.

According to a disclosed class of innovative embodiments, there isprovided: a method for fabricating a semiconductor active device,comprising the actions of: a) patterning a vertically inhomogeneousIII-N semiconductor layer to expose channel areas of first transistorsbut not channel areas of second transistors; b) introducing fluorineinto said channel areas of said first transistors, but substantially notinto said channel areas of said second transistors, to provide differentthreshold voltage values for said first and second transistors; and c)forming sources, drains, and gates, to complete formation of saidtransistors; wherein said action (b) causes said first transistors, butnot said second transistors, to have a positive threshold voltage.

According to a disclosed class of innovative embodiments, there isprovided: A method for fabricating a III-N semiconductor active device,comprising the actions of: forming a first gate electrode pattern, overdesired depletion-mode transistor channel locations, in a verticallyinhomogeneous semiconductor layer having the general composition of(Al_(x)M_((1-x)))Y, where M is predominantly Ga and Y is predominantlyN, and the Al fraction is higher near a surface of said layer;introducing fluorine and forming a second gate electrode pattern, overdesired enhancement-mode transistor channel locations, in a self-alignedcombination of actions; and forming sources, drains, andinterconnections to complete formation of an electrical circuit.

According to a disclosed class of innovative embodiments, there isprovided: an integrated circuit, comprising: enhancement-mode anddepletion-mode transistors, mutually interconnected to form anelectrical circuit; wherein said transistors all have channels formed ina common layer of vertically inhomogeneous Group III nitridesemiconductor material having a higher Al fraction near a surface ofsaid layer; and wherein said enhancement-mode transistors have afluorine concentration, in at least one level of said layer, which ismore than one thousand times the fluorine concentration in acorresponding portion of said layer at said depletion-mode transistors.

MODIFICATIONS AND VARIATIONS

As will be recognized by those skilled in the art, the innovativeconcepts described in the present application can be modified and variedover a tremendous range of applications, and accordingly the scope ofpatented subject matter is not limited by any of the specific exemplaryteachings given.

While the above example describes a lateral device, it is alsocontemplated that the various disclosed inventions can be used in mergeddevices including a lateral transistor element.

It is also contemplated that the disclosed inventions can be applied tosome classes of vertical devices with appropriate changes.

The disclosed technology can also be used to create a merged device, inwhich enhancement and depletion transistors are combined inside a singleisolation area.

For another example, minor variations in the semiconductor composition,e.g. use of a phosphonitride instead of a pure nitride, or use of anAl_(x)Ga_((1-x))N over Al_(y)Ga_((1-y))N heterostructure for the basicHEMT structure, are contemplated as alternatives.

The present innovations provide users with the capability of makingsingle voltage supply RFIC and MMIC. It also provides users a monolithicintegration technology for implementing GaN-based digital integratedcircuits that are needed for high temperature electronics.

For another example, in the various device structures shown, a varietyof materials can optionally be used for gate electrodes (taking intoaccount any resulting differences in work function).

In one contemplated class of embodiments, gate materials with differentwork functions can be used in combination with the trapped sheet chargelayer provided by various embodiments described above, to increase thedifference between the threshold voltages of the two types oftransistors (for a given fluorine dosage). Alternatively, this can beused to achieve four different threshold voltages on a single III-Nchip, if desired.

Similarly, various changes or substitutions can be made in the epitaxiallayer doping.

Similarly, as noted above, various materials can optionally be used forthe substrate.

The methods and structures described above are not only applicable toHEMT or MISHFET devices, but also to III-N MESFET (Metal-semiconductorFET) and MOSFET devices. (MESFET devices do not use a gate insulator,but instead provide a Schottky barrier between gate and channel.)

Additional general background, which helps to show variations andimplementations, may be found in the following publications, all ofwhich are hereby incorporated by reference:

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None of the description in the present application should be read asimplying that any particular element, step, or function is an essentialelement which must be included in the claim scope: THE SCOPE OF PATENTEDSUBJECT MATTER IS DEFINED ONLY BY THE ALLOWED CLAIMS. Moreover, none ofthese claims are intended to invoke paragraph six of 35 USC section 112unless the exact words “means for” are followed by a participle.

The claims as filed are intended to be as comprehensive as possible, andNO subject matter is intentionally relinquished, dedicated, orabandoned.

1. A method for fabricating a semiconductor active device, comprisingthe actions of: a) patterning a vertically inhomogeneous III-Nsemiconductor layer to expose first gate areas of first transistors butnot second gate areas of second transistors; b) introducing fluorineinto said first gate areas, but substantially not into said second gateareas, to provide different threshold voltage values for said firsttransistors and said second transistors; and c) forming sources, drains,and gates, to complete formation of said first transistors and saidsecond transistors; wherein said introducing causes said firsttransistors, but not said second transistors, to have a positivethreshold voltage and modulate the threshold voltage.
 2. The method ofclaim 1, wherein said patterning includes patterning a semiconductorlayer comprising an AlGaN/GaN layered structure.
 3. The method of claim1, wherein said introducing includes introducing fluorine into deviceisolation zones.
 4. The method of claim 1, wherein said introducingincludes self-aligning said fluorine is with locations of said gates. 5.The method of claim 1, wherein said patterning includes patterning asemiconductor layer comprising an epitaxial layer supported by asubstrate of sapphire, silicon, SiC, AlN, or GaN.
 6. The method of claim1, wherein said patterning includes patterning a semiconductor layercomprising an epitaxial structure comprising a nucleation layer of GaNor AlN, a buffer layer of GaN or AlGaN, a GaN channel, and an AlGaNbarrier.
 7. The method of claim 1, wherein said forming said sources andsaid drains comprises depositing multiple metal layers and rapid thermalannealing, wherein said metal layers are selected from the groupconsisting of Ti, Al, Ni, and Au.
 8. The method of claim 1, wherein saidintroducing fluorine into said first gate areas includes subjecting saidfirst gate areas to fluorine-based plasma treatment using a feed gasselected from the group consisting of CF₄, SF₆, BF₃, and mixturesthereof.
 9. The method of claim 1, wherein said forming includes forminga gate electrode by depositing gate metal followed by lift-off or metaletching, using at least one metal selected from the group consisting ofTi, Al, Ni, and Au.
 10. The method of claim 1, further comprisingdepositing, over said first transistors and said second transistors, apassivation material selected from the group consisting of siliconnitride, silicon oxide, polyimide, and benzocyclobutene.
 11. The methodof claim 1, further comprising: subjecting said first transistors andsaid second transistors to thermal annealing at approximately a highesttemperature which will not change a Schottky barrier below the gates.12. The method of claim 1, further comprising: depositing a thin film ofdielectric material on a planar surface of the vertically inhomogeneousIII-N semiconductor layer.
 13. The method of claim 12, wherein saidforming includes forming said gates on said thin film of dielectricmaterial.
 14. The method of claim 1, wherein said forming includesforming said gates directly on said vertically inhomogeneous III-Nsemiconductor layer, without any recess etch.
 15. The method of claim 1,further comprising: forming an additional thin film of dielectricmaterial between said gates and a surface of the verticallyinhomogeneous III-N semiconductor layer.
 16. A method for fabricating aIII-N semiconductor active device, comprising the actions of: forming afirst gate electrode pattern, over selected depletion-mode transistorchannel locations, in a vertically inhomogeneous semiconductor layerhaving a general composition of (AlxM(1-x)Y) where M is predominantly Gaand Y is predominantly N, and an Al fraction is higher near a surface ofsaid layer; introducing fluorine ions and forming a second gateelectrode pattern, over selected enhancement-mode transistor channellocations, in a self-aligned combination of actions, wherein thefluorine ions modulate a threshold voltage; and forming sources, drains,and interconnections to complete formation of an electrical circuit. 17.The method of claim 16, wherein said forming said first gate electrodepattern includes forming said first gate electrode pattern over selecteddepletion-mode transistor channel locations in said verticallyinhomogeneous semiconductor layer, said vertically inhomogeneoussemiconductor layer comprising an epitaxial layer supported by asubstrate of sapphire, silicon, SiC, AlN, or GaN.
 18. The method ofclaim 16, wherein said forming said first gate electrode patternincludes forming said first gate electrode pattern over said selecteddepletion-mode transistor channel locations in said verticallyinhomogeneous semiconductor layer, said vertically inhomogeneoussemiconductor layer comprising an epitaxial structure comprising anucleation layer of GaN or AlN, a buffer layer of GaN or AlGaN, a GaNchannel, and an AlGaN barrier.
 19. The method of claim 16, wherein saidforming said sources, drains and interconnections includes forming saidsources and said drains by depositing multiple metal layers and rapidthermal annealing, wherein said multiple metal layers are selected fromthe group consisting of Ti, Al, Ni, and Au.
 20. The method of claim 16,wherein said introducing fluorine ions includes subjecting saidenhancement mode transistor channel locations to fluorine-based plasmatreatment using a feed gas selected from the group consisting of CF₄,SF₆, BF₃, and mixtures thereof.
 21. The method of claim 16, furthercomprising: forming a gate electrode by depositing a gate metal followedby lift-off or metal etching, using at least one metal selected from thegroup consisting of Ti, Al, Ni, and Au.
 22. The method of claim 16,further comprising depositing, a passivation material selected from thegroup consisting of silicon nitride, silicon oxide, polyimide, andbenzocyclobutene.